The present invention relates to a nonvolatile semiconductor storage device, whose threshold voltage is electrically controlled to store data.
Nonvolatile semiconductor storage devices, such as EEPROM and flash EEPROM, which have floating gates and are electrically rewritable, execute data write and erase by raising and lowering the memory cell threshold voltage Vth with electrical charges injected into or extracted from the floating gates.
FIG. 7 is a circuit diagram showing part of the memory cell array of a conventional nonvolatile semiconductor storage device. This memory cell array is constructed of memory cells M11, M12, M21, M22 arranged in a matrix form. The memory cells M11, M12; M21, M22, which are located on same rows, are connected respectively to word lines WL1; WL2, which share a common control gate. The memory cells M11, M21; M12, M22, which are located on same columns, are connected respectively to bit lines BL1; BL2, which share a common drain. Moreover, the sources of all the memory cells M11, M12, M21, M22 are connected to a common source line SL.
When erasing data in the aforementioned memory cell array, a negative voltage of, for example, −10 V is applied to the word lines WL1 and WL2, a positive voltage of, for example, 5 V is applied to the source line SL, and the bit lines BL1, BL2 are put into a high impedance state. Then, in the memory cells M11, M12, M21, M22, electrons are discharged from the floating gate to the source due to an FN tunneling effect, and the threshold voltage is lowered to attain an erase state.
On the other hand, when writing data, a positive high voltage of, for example, 12 V is applied to the word line connected to the selection memory cell to be subjected to write, and the other word lines are grounded. A positive voltage of, for example, 6 V is applied to the bit line connected to the selection memory cell for a prescribed time, and the other bit lines are grounded. Then, in the selection memory cell, electrons (hot electrons) are injected into the floating gate from a channel region formed between the source and drain diffusion layers, and the threshold voltage rises to attain a written state in which data are stored.
In general, the threshold voltage during write is set at a prescribed value by repetitively applying a write pulse of a constant pulse width to the bit line connected to the selection memory cell, thereafter detecting the threshold voltage of the selection memory cell by means of a sense circuit and ending the write operation when the detected threshold voltage falls within a prescribed range.
The threshold voltage of the memory cell has a tendency to change in proportion to the logarithmic value of the width of the pulse applied to the memory cell. If the write pulse of same pulse width is repetitively applied, then the change in the threshold voltage of the memory cell saturates and gradually reduces. Accordingly, there is a problem that the write pulse applying frequency is required to be increased to change the threshold voltage up to the prescribed threshold voltage Vth and the write time becomes long. Moreover, write and verify are repetitively executed since each write is followed by the so-called verify operation for confirming whether or not the threshold voltage has reached the prescribed value consuming a prescribed time, and this leads to a further problem that a total time required for the write becomes long if the write pulse applying frequency is increased.
Furthermore, in the case of a multi-valued memory, a low operating voltage memory or the like, the distribution width of the required threshold voltage is narrow. Therefore, if it is attempted to restrain the threshold value distribution, the pulse width at one time becomes small. Therefore, the write is required to be executed by applying the pulse many times in order to attain the required threshold value, and this leads to a long write time.
Accordingly, the following prior art examples have been proposed as a technique for narrowing the threshold voltage distribution without increasing the write time.
According to Japanese Patent Laid-Open Publication Nos. HEI 7-73685 and HEI 11-73786, the frequency of applying the write pulse is reduced by increasing the write pulse width in accordance with an increase in the frequency of repetition.
In Japanese Patent Laid-Open Publication No. HEI 10-177795, the write time is shortened by increasing the pulse width at a prescribed rate of increase until the threshold voltage reaches a prescribed range inclusive of the target value, reducing the rate of increase in the pulse width after the threshold voltage reaches the prescribed range and repetitively applying the pulse until the threshold voltage reaches the target value Vth or its neighborhood.
According to Japanese Patent Laid-Open Publication No. HEI 11-39887, the ISPP (Incremental Step Pulse Programming) method of changing the level of a voltage applied to the selection memory cell as the frequency of write increases is improved to apply a write pulse of a large width at the first time and apply a pulse, which has a small width and of which the voltage level gradually increases as the frequency of write increases, at the second and subsequent times.
Furthermore, Japanese Patent Laid-Open Publication Nos. HEI 11-96785, 2000-113686 and 2000-123584 propose the methods of determining the memory cell characteristics, setting the pulse width or the pulse voltage of the write pulse optimum for the memory cell characteristics and applying a write pulse optimum for each memory cell. According to Japanese Patent Laid-Open Publication No. HEI 11-96785, on the basis of an A*2B pulse width system obtained by improving an exponential power pulse write system set so that the write time at the first time is comparatively long and a cumulative write time increases at a ratio of exponential power at the second and subsequent times, the value of A and the value of B (<1) can be adjusted according to the memory cell characteristics.
Moreover, the cumulative write time is reduced by adopting the power pulse write system when an overhead time including a verify time is sufficiently longer than one write time and adopting a uniform pulse write system when the overhead time is sufficiently shorter than one write time.
The conventional methods, which are described in the preceding two paragraphs and reduce the write time by changing the write pulse width or pulse voltage in order to complete the write within the smallest possible number of times, have the problems as follows.
That is, the prior art example of Japanese Patent Laid-Open Publication No. HEI 11-39887 discloses the change in the pulse width or the pulse voltage of the write pulse, but the method discloses no concrete write pulse width determining method.
According to Japanese Patent Laid-Open Publication No. HEI 11-96785, the pulse width or the pulse voltage of the write pulse optimum for the memory cell M characteristics is set, and the various parameters of an initial value, a modulo value and so on for setting the write pulse width are set in the fuse array. However, there is described neither a concrete method nor a procedure regarding how to set the write pulse width in this fuse array according to the characteristic variations of the memory cells.
According to Japanese Patent Laid-Open Publication No. 2000-113686, the write pulse of a prescribed width is applied to each memory cell before the write operation, and the change in the threshold value is measured to determine the practical write pulse width. However, erase is needed again to bring each memory cell back into the original state, and the write time eventually becomes long. Moreover, the write characteristic of a sample for evaluation is used to set the pulse width of the write pulse optimum for the memory cell characteristics. However, no measuring method of the write characteristic is concretely disclosed.
Japanese Patent Laid-Open Publication No. 2000-123584 describes the correction of the write voltage according to the memory cell characteristics. However, since no quantitative correction method is disclosed, the quantity of correction cannot help being determined according to the read result after write, and the superfluous processing of determining the quantity of correction is added, resulting in increasing the write time.
As described above, the prior art technologies do not always intend to attain the target threshold value with the first-time write pulse. Moreover, the conventional method of repeating the write and verify many times with a short pulse has had the problem that an error between the cumulative write time and the write time when write is executed with one pulse at one time has been large.